/*
 * Copyright (c) Huawei Technologies Co., Ltd. 2019-2022. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * Description:
 * Author: huawei
 * Create: 2019-10-15
 */

#ifndef HILINK_SUBCTRL_REG_OFFSET_FIELD_H
#define HILINK_SUBCTRL_REG_OFFSET_FIELD_H

#define HILINK_SUBCTRL_0_BIT0_LEN 2
#define HILINK_SUBCTRL_0_BIT0_OFFSET 0

#define HILINK_SUBCTRL_1_BIT0_LEN 12
#define HILINK_SUBCTRL_1_BIT0_OFFSET 0

#define HILINK_SUBCTRL_2_BIT0_LEN 4
#define HILINK_SUBCTRL_2_BIT0_OFFSET 0

#define HILINK_SUBCTRL_3_BIT0_LEN 2
#define HILINK_SUBCTRL_3_BIT0_OFFSET 0

#define HILINK_SUBCTRL_4_BIT0_LEN 2
#define HILINK_SUBCTRL_4_BIT0_OFFSET 0

#define HILINK_SUBCTRL_5_BIT0_LEN 2
#define HILINK_SUBCTRL_5_BIT0_OFFSET 0

#define HILINK_SUBCTRL_6_BIT0_LEN 1
#define HILINK_SUBCTRL_6_BIT0_OFFSET 0

#define HILINK_SUBCTRL_7_BIT4_LEN 4
#define HILINK_SUBCTRL_7_BIT4_OFFSET 4
#define HILINK_SUBCTRL_7_BIT0_LEN 4
#define HILINK_SUBCTRL_7_BIT0_OFFSET 0

#define HILINK_SUBCTRL_8_BIT28_LEN 4
#define HILINK_SUBCTRL_8_BIT28_OFFSET 28
#define HILINK_SUBCTRL_8_BIT24_LEN 4
#define HILINK_SUBCTRL_8_BIT24_OFFSET 24
#define HILINK_SUBCTRL_8_BIT20_LEN 4
#define HILINK_SUBCTRL_8_BIT20_OFFSET 20
#define HILINK_SUBCTRL_8_BIT16_LEN 4
#define HILINK_SUBCTRL_8_BIT16_OFFSET 16
#define HILINK_SUBCTRL_8_BIT12_LEN 4
#define HILINK_SUBCTRL_8_BIT12_OFFSET 12
#define HILINK_SUBCTRL_8_BIT8_LEN 4
#define HILINK_SUBCTRL_8_BIT8_OFFSET 8
#define HILINK_SUBCTRL_8_BIT4_LEN 4
#define HILINK_SUBCTRL_8_BIT4_OFFSET 4
#define HILINK_SUBCTRL_8_BIT0_LEN 4
#define HILINK_SUBCTRL_8_BIT0_OFFSET 0

#define HILINK_SUBCTRL_9_BIT0_LEN 2
#define HILINK_SUBCTRL_9_BIT0_OFFSET 0

#define HILINK_SUBCTRL_10_BIT20_LEN 4
#define HILINK_SUBCTRL_10_BIT20_OFFSET 20
#define HILINK_SUBCTRL_10_BIT16_LEN 4
#define HILINK_SUBCTRL_10_BIT16_OFFSET 16
#define HILINK_SUBCTRL_10_BIT8_LEN 4
#define HILINK_SUBCTRL_10_BIT8_OFFSET 8
#define HILINK_SUBCTRL_10_BIT4_LEN 4
#define HILINK_SUBCTRL_10_BIT4_OFFSET 4
#define HILINK_SUBCTRL_10_BIT0_LEN 4
#define HILINK_SUBCTRL_10_BIT0_OFFSET 0

#define HILINK_SUBCTRL_11_BIT2_LEN 1
#define HILINK_SUBCTRL_11_BIT2_OFFSET 2
#define HILINK_SUBCTRL_11_BIT0_LEN 2
#define HILINK_SUBCTRL_11_BIT0_OFFSET 0

#define HILINK_SUBCTRL_12_BIT10_LEN 2
#define HILINK_SUBCTRL_12_BIT10_OFFSET 10
#define HILINK_SUBCTRL_12_BIT8_LEN 2
#define HILINK_SUBCTRL_12_BIT8_OFFSET 8
#define HILINK_SUBCTRL_12_BIT6_LEN 2
#define HILINK_SUBCTRL_12_BIT6_OFFSET 6
#define HILINK_SUBCTRL_12_BIT4_LEN 2
#define HILINK_SUBCTRL_12_BIT4_OFFSET 4
#define HILINK_SUBCTRL_12_BIT2_LEN 2
#define HILINK_SUBCTRL_12_BIT2_OFFSET 2
#define HILINK_SUBCTRL_12_BIT0_LEN 2
#define HILINK_SUBCTRL_12_BIT0_OFFSET 0

#define HILINK_SUBCTRL_13_BIT0_LEN 4
#define HILINK_SUBCTRL_13_BIT0_OFFSET 0

#define HILINK_SUBCTRL_14_BIT0_LEN 4
#define HILINK_SUBCTRL_14_BIT0_OFFSET 0

#define HILINK_SUBCTRL_15_BIT8_LEN 1
#define HILINK_SUBCTRL_15_BIT8_OFFSET 8
#define HILINK_SUBCTRL_15_BIT0_LEN 8
#define HILINK_SUBCTRL_15_BIT0_OFFSET 0

#define HILINK_SUBCTRL_16_BIT4_LEN 4
#define HILINK_SUBCTRL_16_BIT4_OFFSET 4
#define HILINK_SUBCTRL_16_BIT0_LEN 4
#define HILINK_SUBCTRL_16_BIT0_OFFSET 0

#define HILINK_SUBCTRL_17_BIT0_LEN 4
#define HILINK_SUBCTRL_17_BIT0_OFFSET 0

#define HILINK_SUBCTRL_18_BIT4_LEN 4
#define HILINK_SUBCTRL_18_BIT4_OFFSET 4
#define HILINK_SUBCTRL_18_BIT0_LEN 4
#define HILINK_SUBCTRL_18_BIT0_OFFSET 0

#define HILINK_SUBCTRL_19_BIT0_LEN 4
#define HILINK_SUBCTRL_19_BIT0_OFFSET 0

#define HILINK_SUBCTRL_20_BIT4_LEN 4
#define HILINK_SUBCTRL_20_BIT4_OFFSET 4
#define HILINK_SUBCTRL_20_BIT0_LEN 4
#define HILINK_SUBCTRL_20_BIT0_OFFSET 0

#define HILINK_SUBCTRL_21_BIT0_LEN 2
#define HILINK_SUBCTRL_21_BIT0_OFFSET 0

#define HILINK_SUBCTRL_22_BIT2_LEN 2
#define HILINK_SUBCTRL_22_BIT2_OFFSET 2
#define HILINK_SUBCTRL_22_BIT0_LEN 2
#define HILINK_SUBCTRL_22_BIT0_OFFSET 0

#define HILINK_SUBCTRL_23_BIT0_LEN 1
#define HILINK_SUBCTRL_23_BIT0_OFFSET 0

#define HILINK_SUBCTRL_24_BIT1_LEN 1
#define HILINK_SUBCTRL_24_BIT1_OFFSET 1
#define HILINK_SUBCTRL_24_BIT0_LEN 1
#define HILINK_SUBCTRL_24_BIT0_OFFSET 0

#define HILINK_SUBCTRL_25_BIT8_LEN 14
#define HILINK_SUBCTRL_25_BIT8_OFFSET 8
#define HILINK_SUBCTRL_25_BIT0_LEN 7
#define HILINK_SUBCTRL_25_BIT0_OFFSET 0

#define HILINK_SUBCTRL_26_BIT1_LEN 1
#define HILINK_SUBCTRL_26_BIT1_OFFSET 1
#define HILINK_SUBCTRL_26_BIT0_LEN 1
#define HILINK_SUBCTRL_26_BIT0_OFFSET 0

#define HILINK_SUBCTRL_27_BIT1_LEN 1
#define HILINK_SUBCTRL_27_BIT1_OFFSET 1
#define HILINK_SUBCTRL_27_BIT0_LEN 1
#define HILINK_SUBCTRL_27_BIT0_OFFSET 0

#define HILINK_SUBCTRL_28_BIT8_LEN 11
#define HILINK_SUBCTRL_28_BIT8_OFFSET 8
#define HILINK_SUBCTRL_28_BIT0_LEN 7
#define HILINK_SUBCTRL_28_BIT0_OFFSET 0

#define HILINK_SUBCTRL_29_BIT1_LEN 1
#define HILINK_SUBCTRL_29_BIT1_OFFSET 1
#define HILINK_SUBCTRL_29_BIT0_LEN 1
#define HILINK_SUBCTRL_29_BIT0_OFFSET 0

#define HILINK_SUBCTRL_30_BIT1_LEN 1
#define HILINK_SUBCTRL_30_BIT1_OFFSET 1
#define HILINK_SUBCTRL_30_BIT0_LEN 1
#define HILINK_SUBCTRL_30_BIT0_OFFSET 0

#define HILINK_SUBCTRL_31_BIT0_LEN 32
#define HILINK_SUBCTRL_31_BIT0_OFFSET 0

#define HILINK_SUBCTRL_32_BIT0_LEN 32
#define HILINK_SUBCTRL_32_BIT0_OFFSET 0

#define HILINK_SUBCTRL_33_BIT0_LEN 32
#define HILINK_SUBCTRL_33_BIT0_OFFSET 0

#define HILINK_SUBCTRL_34_BIT0_LEN 32
#define HILINK_SUBCTRL_34_BIT0_OFFSET 0

#define HILINK_SUBCTRL_35_BIT0_LEN 32
#define HILINK_SUBCTRL_35_BIT0_OFFSET 0

#define HILINK_SUBCTRL_36_BIT0_LEN 32
#define HILINK_SUBCTRL_36_BIT0_OFFSET 0

#define HILINK_SUBCTRL_37_BIT0_LEN 32
#define HILINK_SUBCTRL_37_BIT0_OFFSET 0

#define HILINK_SUBCTRL_38_BIT0_LEN 32
#define HILINK_SUBCTRL_38_BIT0_OFFSET 0

#define HILINK_SUBCTRL_39_BIT0_LEN 32
#define HILINK_SUBCTRL_39_BIT0_OFFSET 0

#endif // __HILINK_SUBCTRL_REG_OFFSET_FIELD_H__
